micron_biased_U3 errors= 8
micron_biased_U1 errors= 0
microchip_biased_U3 errors= 4938
infineon_biased_U3 errors= 1977677
infineon_unbiased_U4 errors= 11
infineon_biased_U1 errors= 242
giga_biased_U2 errors= 2092
micron_unbiased_U6 errors= 3
renesas_unbiased_U6 errors= 994
micron_biased_U2 errors= 0
infineon_biased_U2 errors= 182
giga_unbiased_U4 errors= 1786
giga_biased_U3 errors= 2092
infineon_unbiased_U6 errors= 428
microchip_biased_U1 errors= 368
winbond_unbiased_U4 errors= 2645
giga_unbiased_U5 errors= 2333
renesas_biased_U3 errors= 63422
winbond_unbiased_U6 errors= 3735
renesas_biased_U2 errors= 60611
giga_biased_U1 errors= 4792
renesas_biased_U1 errors= 62482
renesas_unbiased_U5 errors= 1296
infineon_unbiased_U5 errors= 458
microchip_biased_U2 errors= 1975830
micron_unbiased_U4 errors= 258
micron_unbiased_U5 errors= 157
microchip_unbiased_U4 errors= 508
winbond_biased_U3 errors= 3991
winbond_biased_U2 errors= 631826
renesas_unbiased_U4 errors= 888
microchip_unbiased_U5 errors= 279
winbond_biased_U1 errors= 2550
giga_unbiased_U6 errors= 2221